module io_tp (
    D,
    Q,
    CLK1,
    CLK_OUT,
    CLK_OUT2,

    flash_sck,
    flash_cs,
    flash_io,

    JTDI,
    JTMS,
    JTCK,
    JTDO
);

    input wire D;
    output wire Q;
    input wire CLK1;
    output wire CLK_OUT;
    output wire CLK_OUT2;
    assign Q = ~D;
    assign CLK_OUT = ~CLK1;
    reg [15:0] count = 'd0;
    assign CLK_OUT2 = count[1];

    def_clk clk(CLK1,clk_in);


    always @(posedge clk_in) begin
        count <= count + 16'd1;
    end

    output wire     flash_sck;
    output wire     flash_cs;
    inout wire[3:0] flash_io;

    //assign flash_sck = count[1];

    //定义双向IO
    //alta_io flash_io0(.padio(),.datain(),.oe(),.combout());
    alta_io flash_io0(.padio(flash_io[0]),.datain(FLASH_IO0_SI)     ,.oe(FLASH_SI_OE),   .combout(FLASH_IO0_SI_i)    );
    alta_io flash_io1(.padio(flash_io[1]),.datain(FLASH_IO1_SO)     ,.oe(FLASH_SO_OE),   .combout(FLASH_IO1_SO_i)    );
    alta_io flash_io2(.padio(flash_io[2]),.datain(FLASH_IO2_WPn)    ,.oe(WPn_IO2_OE),    .combout(FLASH_IO2_WPn_i)   );
    alta_io flash_io3(.padio(flash_io[3]),.datain(FLASH_IO3_HOLDn)  ,.oe(HOLDn_IO3_OE),  .combout(FLASH_IO3_HOLDn_i) );

    input JTDI;
    input JTMS;
    input JTCK;
    output JTDO;

    wire[7:0] GPIO0_I = 'h55;
    wire[7:0] GPIO1_I = 'h55;
    wire[7:0] GPIO2_I = 'h55;
    wire[7:0] GPIO0_O;
    wire[7:0] GPIO1_O;
    wire[7:0] GPIO2_O;
    wire[7:0] nGPEN0;
    wire[7:0] nGPEN1;
    wire[7:0] nGPEN2;

 /*设置flash的位置*/
defparam mcu.FLASH_BIAS = 24'h80000;
    //有关软核的使用
    alta_mcu mcu(
        //需要设置定值
        .EXT_RAM_EN (1'b0),
        .HRESP_EXT (2'b00),
        .CLK(clk_in),

        //JTAG 接口
        .JTDO(JTDO),
        .JTDI(JTDI),
        .JTCK(JTCK),
        .JTMS(JTMS),

        /*GPIO*/
    /*input [7:0]  */ .GPIO0_I(GPIO0_I),
    /*input [7:0]  */ .GPIO1_I(GPIO1_I),
    /*input [7:0]  */ .GPIO2_I(GPIO2_I),
    /*output [7:0] */ .GPIO0_O(GPIO0_O),
    /*output [7:0] */ .GPIO1_O(GPIO1_O),
    /*output [7:0] */ .GPIO2_O(GPIO2_O),
    /*output [7:0] */ .nGPEN0 (nGPEN0 ),
    /*output [7:0] */ .nGPEN1 (nGPEN1 ),
    /*output [7:0] */ .nGPEN2 (nGPEN2 ),


    //连接flash
    /*output */ .FLASH_SCK(flash_sck),
    /*output */ .FLASH_CS_n(flash_cs),
//inouts
    //flash
    /*output*/ .FLASH_IO0_SI(FLASH_IO0_SI),
    /*output*/ .FLASH_IO1_SO(FLASH_IO1_SO),
    /*output*/ .FLASH_IO2_WPn(FLASH_IO2_WPn),
    /*output*/ .FLASH_IO3_HOLDn(FLASH_IO3_HOLDn),
    /*input */ .FLASH_IO0_SI_i(FLASH_IO0_SI_i),
    /*input */ .FLASH_IO1_SO_i(FLASH_IO1_SO_i),
    /*input */ .FLASH_IO2_WPn_i(1'b1),
    /*input */ .FLASH_IO3_HOLDn_i(1'b1),
    /*output*/ .FLASH_SI_OE(FLASH_SI_OE),
    /*output*/ .FLASH_SO_OE(FLASH_SO_OE),
    /*output*/ .WPn_IO2_OE(WPn_IO2_OE),
    /*output*/ .HOLDn_IO3_OE(HOLDn_IO3_OE)
    );

endmodule